This invention relates to an operation control system, and more particularly to a system having a parity error detection function to detect abnormality of input-output data.
FIG. 1 shows a conventional data processing system 8, including a plurality of devices 10, 12, 14, and 18 interconnected by an external bus 16, for processing data subject to a parity error detection function As is well known in the art, a parity error detection function includes a parity generation operation by a device transmitting data, consisting of generating a parity bit from the data being transmitted, and a parity check operation by a device receiving data, consisting of generating a parity bit from the received data and comparing it to the parity bit generated by the device transmitting the data. In system 8, when input and output of data is performed by controlling a process input-output device 10 or external devices 12 and 14 through an external bus etc. by a main control device 18, the following parity check is performed. First of all, on data collection from main control device 18, device 18 sends a collection command through command signal line 20 directing process input-output device 10 or external device 12 or 14 to collect the data. In response, process input-output device 10 or external device 12 or 14, that received the collect command, sends the data to external bus 16, generates a parity bit in accordance with the prescribed function by a parity generating circuit 28, 30, or 32 of a respective interface 22 that is incorporated or connected thereto, and sends the party bit as a parity signal over a parity signal line 24. Thereupon, main control device 18 that has received collected data from external bus 16 and the parity signal of parity signal line 24 generates a parity bit by a parity detection circuit of a parity circuit 26, in accordance with the prescribed function from the collected data received. Main control device 18 then compares the generated parity bit with the received parity signal and makes a decision as to whether or not a parity error occurred on the transmission over bus 16.
On the other hand, during a data output operation from main control device 18, i.e. during a write parity check, main control device 18 sends an output command through command signal line 20 to process input-output device 10 or external device 12 or 14 that is trying to output data, then generates a parity bit by means of parity generating circuit 26 in accordance with the prescribed function from the output data, simultaneously with output of data through external bus 16, and sends this to parity signal line 24 as a parity signal. Thereupon, process input-output device 10 or external device 12 or 14 that has received the output command generates, by means of a parity detecting circuit of a respective interface 22 that is incorporated or connected thereto, a parity bit in accordance with the prescribed function from the received data, and performs a decision as to whether or not there is an abnormality by comparing it with the parity signal received from parity signal line 24.
In this way, conventionally, for process input-output device 10 connected to external bus 16, interface 22 is required having a parity circuit 28 consisting of parity generating and detecting circuit, which matches the parity check function in main control device 18. Similarly, in a conventional system external devices 12 and 14 require corresponding parity circuit 30 and 32 which match the parity check function in main control device 18.
As described above, in conventional systems interconnected via an external bus 16, main control device 18 having a specified parity check function requires corresponding purity circuits having identical parity check functions. Thus equipment having parity circuits using different parity check functions or equipment having no parity circuit can not be used on the same bus. Consequently, limitations are imposed on system architecture, and a flexible architecture can not be achieved.